By Francisco Serra-Graells
Low-Voltage CMOS Log Companding Analog Design offers in element state of the art analog circuit ideas for the very low-voltage and low-power layout of systems-on-chip in CMOS applied sciences. The proposed method is principally in line with bases: the instant Log Companding idea, and the MOSFET working within the subthreshold area. the previous permits internal compression of the voltage dynamic-range for terribly low-voltage operation, whereas the latter is appropriate with CMOS applied sciences and compatible for low-power circuits. the mandatory history at the particular modeling of the MOS transistor for Companding is provided at first. Following this normal procedure, an entire set of CMOS uncomplicated construction blocks is proposed and analyzed for a wide selection of analog sign processing. particularly, the coated parts contain: amplification and AGC, arbitrary filtering, PTAT new release, and pulse period modulation (PDM). for every subject, numerous case reviews are thought of to illustrate the layout technique. additionally, built-in examples in 1.2um and 0.35um CMOS applied sciences are suggested to make sure the great contract among layout equations and experimental information. The ensuing analog circuit topologies convey very low-voltage (i.e. 1V) and low-power (few tenths of uA) services. except those particular layout examples, a true business program within the box of listening to aids is additionally offered because the major demonstrator of all of the proposed simple development blocks. This system-on-chip indicates real 1V operation, excessive flexibility via electronic programmability and extremely low-power intake (about 300uA together with the Class-D amplifier). As a consequence, the suggested ASIC can meet the requisites of an entire kinfolk of universal listening to reduction types. In end, this e-book is addressed to either ASIC designers who can observe its contents to the synthesis of very low-power systems-on-chip in normal CMOS applied sciences, in addition to to the lecturers of recent circuit layout in digital engineering.
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